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Interface Descriptions
Backend Interface
The backend interface supports both synchronous operation (to the core clock) and asynchronous
operation to backend devices ( Table 3-5 ).
Table 3-5 ? Backend Signals
Port Name
Type
Description
MEMREQn
Out Memory Request (active low) output. The backend interface requires memory
access completion within 10 μs of MEMREQ going LOW to avoid data loss or
overrun on the 1553B interface.*
MEMGNTn
In
Memory Grant (active low) input. This input should be synchronous to CLK and
needs to meet the internal register setup time. This input can be held LOW if
the core has continuous access to the RAM.
MEMWRn
MEMRDn
MEMCSn
Out Memory Write (active low)
Synchronous mode: This output indicates that data is to be written on the rising
clock edge.
Asynchronous mode: This output will be LOW for a minimum of one clock
period and can be extended by the MEMWAITn input. The address and data
are valid one clock cycle before MEMWRn is active and held for one clock
cycle after MEMWRn goes inactive.
Out Memory Read (active low)
Synchronous mode: This output indicates that data will be read on the next
rising clock edge. This signal is intended as the read signal for synchronous
RAMs.
Asynchronous mode: This output will be LOW for a minimum of one clock
period and can be extended by the MEMWAITn input. The address is valid one
clock cycle before MEMRDn is active and held for one clock cycle after
MEMRDn goes inactive. The data is sampled as MEMRDn goes HIGH.
Out Memory Chip Select (active low). This output has the same timing as
MEMADDR.
MEMWAITn
In
Memory Wait (active low)
Synchronous mode: This input is not used; it should be tied HIGH.
Asynchronous mode: Indicates that the backend is not ready, and the core
should extend the read or write strobe period. This input should be
synchronous to CLK and needs to meet the internal register setup time. It can
be permanently held HIGH.
MEMOPER[1:0]
Out Indicates the type of memory access being performed.
00: Data transfer for both data and mode code transfers
01: TSW
10: Command word
11: Not used
MEMADDR[10:0] Out Memory Address output (the subaddress mapping is covered in "Standard
MEMDOUT[15:0] Out Memory Data output
MEMDIN[15:0]
In
Memory Data input
Note: *The 10 μs refers to the time from MEMREQn being asserted to the core deasserting its
MEMREQn signal. The core has an internal overhead of five clock cycles, and any inserted wait
cycles will also reduce this time. This time increases to 19.5 μs if the WRTTSW and WRTCMD
inputs are LOW.
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